Performance Comparison of Charge-Shared Matchline Sensing Schemes in High-Speed Ternary Content Addressable Memory (TCAM)

Kadir, Raqqib Bin; Haque, Muntasim-Ul-; Anwar, Ahmed Selim

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dc.contributor.author	Kadir, Raqqib Bin
dc.contributor.author	Haque, Muntasim-Ul-
dc.contributor.author	Anwar, Ahmed Selim
dc.date.accessioned	2021-10-01T06:14:08Z
dc.date.available	2021-10-01T06:14:08Z
dc.date.issued	2014-10-15
dc.identifier.citation	1. T. Kohonen, Content-Addressable Memories, 2nd ed. New York: Springer-Verlag, 1987. 2. L. Chisvin and R. J. Duckworth, “Content-addressable and associative memory: alternatives to the ubiquitous RAM,” IEEE Computer, vol. 22, no. 7, pp. 51–64, Jul. 1989. 3. K. E. Grosspietsch, “Associative processors and memories: a survey,” IEEE Micro, vol. 12, no. 3, pp. 12–19, Jun. 1992. N. Robinson, “Pattern-addressable memory,” IEEE Micro, vol. 12, no.3, pp. 20–30, Jun. 1992. 4. S. Stas, “Associative processing with CAMs,” in Northcon/93 Conf. Record, 1993, pp. 161–167. 5. S. Stas, “Associative processing with CAMs,” in Northcon/93 Conf. Record, 1993, pp. 161–167. 6. M. Meribout, T. Ogura, and M. Nakanishi, “On using the CAM concept for parametric curve extraction, IEEE Trans. Image Process” vol.9,no.12, pp. 2126–2130, Dec. 2000. 7. M. Nakanishi and T. Ogura, “Real-time CAM-based Hough transform and its performance evaluation,” Machine Vision Appl., vol. 12, no. 2, pp. 59–68, Aug. 2000. 8. E. Komoto, T. Homma, and T. Nakamura, “A high-speed and compact-size JPEG Huffman decoder using CAM,” in Symp. VLSI Circuits Dig. Tech. Papers, 1993, pp. 37–38. 9. L.-Y. Liu, J.-F. Wang, R.-J. Wang, and J.-Y. Lee, “CAM-based VLSI architectures for dynamic Huffman coding,” IEEE Trans. Consumer Electron., vol. 40, no. 3, pp. 282–289, Aug. 1994. 10. B. W. Wei, R. Tarver, J.-S. Kim, and K. Ng, “A single chip Lempel-Ziv data compressor,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol.3, 1993, pp. 1953–1955. 11. R.-Y. Yang and C.-Y. Lee, “High-throughput data compressor designs using content addressable memory,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 4, 1994, pp. 147–150. 38 12. C.-Y. Lee and R.-Y. Yang, “High-throughput data compressor designs using content addressable memory,” IEE Proc.—Circuits, Devices and Syst., vol. 142, no. 1, pp. 69–73, Feb. 1995. 13. D. J. Craft, “A fast hardware data compression algorithm and some algorithmic extensions,” IBM J. Res. Devel., vol. 42, no. 6, pp. 733–745, Nov. 1998. 14. S. Panchanathan and M. Goldberg, “A content-addressable memory architecture for image coding using vector quantization,” IEEE Trans. Signal Process. vol. 39, no. 9, pp. 2066–2078, Sep. 1991. 15. T.-B. Pei and C. Zukowski, “VLSI implementation of routing tables: tries and CAMs,” in Proc. IEEE INFOCOM, vol. 2, 1991, pp. 515–524. 16. “Putting routing tables in silicon”, IEEE Network Mag., vol. 6, no.1, pp. 42–50, Jan. 1992. 17. A. J. McAuley and P. Francis, “Fast routing table lookup using CAMs,” in Proc. IEEE INFOCOM, vol. 3, 1993, pp. 1282–1391. 18. N.-F. Huang, W.-E. Chen, J.-Y. Luo, and J.-M. Chen, “Design of multi-field IPv6 packet classifiers using ternary CAMs,” in Proc. IEEE GLOBECOM, vol. 3, 2001, pp. 1877–1881. 19. G. Qin, S. Ata, I. Oka, and C. Fujiwara, “Effective bit selection methods for improving performance of packet classifications on IP routers,” in Proc. IEEE GLOBECOM, vol. 2, 2002, pp. 2350–2354. 20. H. J. Chao, “Next generation routers,” Proc. IEEE, vol. 90, no. 9, pp. 1518–1558, Sep. 2002.	en_US
dc.identifier.uri	http://hdl.handle.net/123456789/1058
dc.description	Supervised by Dr. Syed Iftekhar Ali, Associate Professor, Department of Electrical and Electronic Engineering (EEE), Islamic University of Technology (IUT), Board Bazar, Gazipur-1704, Bangladesh.	en_US
dc.description.abstract	Ternary content addressable memory (TCAM) is a memory that offers high speed table look-up capability for applications such as internet protocol (IP) packet forwarding and classification in network routers. A performance comparison between different Matchline sensing schemes in high speed Ternary content addressable memory (TCAM) is presented in this thesis. With the conventional current race scheme two different charge shared schemes are being compared. By segmentation of Matchline and then charge sharing reduces the power to some extent. This two charge shared schemes also improves search time and voltage margin. Simulations are performed using 180nm 1.8V CMOS logic in HSPICE. By changing the properties of different transistors, the simulated outputs were compared for better performance measurements.	en_US
dc.language.iso	en	en_US
dc.publisher	Department of Electrical and Electronic Engineering, Islamic University of Technology (IUT), Board Bazar, Gazipur-1704, Bangladesh	en_US
dc.title	Performance Comparison of Charge-Shared Matchline Sensing Schemes in High-Speed Ternary Content Addressable Memory (TCAM)	en_US
dc.type	Thesis	en_US