Performance Comparison of Positive-Feedback Match-Line Sensing Schemes in High Speed Ternary Content Addressable Memory (TCAM)

Abstract

We survey different schemes in the design of TCAM. A TCAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. TCAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main TCAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review TCAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review four methods for reducing power consumption. In our thesis 16×16 bit TCAM is designed in 0.18μm CMOS. The proposed ML sense scheme reduces power consumption by minimizing search time and limiting voltage swing of MLs. In our simulation we used 1.8V supply voltage.