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dc.contributor.author | Rahaman, Md. Istiaque | |
dc.contributor.author | Islam, Iftekharul | |
dc.contributor.author | Galib, Md. Mehedi Hassan | |
dc.date.accessioned | 2022-01-14T08:06:16Z | |
dc.date.available | 2022-01-14T08:06:16Z | |
dc.date.issued | 2012-11-15 | |
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Solid-State Circuits, vol. 40, no. 1, pp. 254–260, Jan. 2005. [6] H. Miyatake, M. Tanaka, and Y. Mori, “A design for high-speed lowpower CMOS fully parallel content-addressable memory macros,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 956–968, Jun. 2001. [7] S. Liu, F. Wu, and J. B. Kuo, “A novel low-voltage content-addressable memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 712–716, Apr. 2001. [8] G. Thirugnanam, N. Vijaykrishnan, and M. J. Irwin, “A novel low power CAM design,” in Proc. 14th Annu. IEEE ASIC/SOC Conf., 2001, pp. 198–202. [9] G. Thirugnanam, N. Vijaykrishnan, and M. J. Irwin, “A novel low power CAM design,” in Proc. 14th Annu. IEEE ASIC/SOC Conf., 2001, pp. 198–202. [10] K. J. Schultz, F. Shafai, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, “Fully parallel 25 MHz, 2.5-Mb CAM,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 1998, pp. 332–333. [11] F. Shafai, K. J. Schultz, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, “Fully parallel 30-MHz, 2.5-Mb CAM,” IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1690–1696, Nov. 1998. [12] G. Kasai,Y. Takarabe, K. Furumi, and M.Yoneda, “200 MHz/200 MSPS 3.2 W at 1.5 V Vdd, 9.4 Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2003, pp. 387–390. 65 [13] M. M. Khellah and M. Elmasry, “Use of charge sharing to reduce energy consumption in wide fan-in gates,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 2, 1998, pp. 9–12. [14] A. Roth, D. Foss, R. McKenzie, and D. Perry, “Advanced ternary CAM circuits on 0.13 _m logic process technology,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2004, pp. 465–468. [15] I. Y.-L. Hsiao, D.-H. Wang, and C.-W. Jen, “Power modeling and low-power design of content addressable memories,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 4, 2001, pp. 926–929. [16] A. Efthymiou and J. D. Garside, “An adaptive serial-parallel CAM architecture for lowpower cache blocks,” in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), 2002, pp. 136–141. [17] , “A CAM with mixed serial-parallel comparison for use in low energy caches,” IEEE Trans. VLSI Syst., vol. 12, no. 3, pp. 325–329, Mar. 2004. [18] N. Mohan and M. Sachdev, “Low power dual matchline content addressable memory,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 2, 2004, pp. 633–636. [19] K.-H. Cheng, C.-H.Wei, and S.-Y. Jiang, “Static divided word matchline line for low-power content addressable memory design,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 2, 2004, pp. 629–632. [20] K. Pagiamtzis and A. Sheikholeslami, “Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2003, pp. 383–386. [21] --- ---, “A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1512–1519, Sep. 2004. [22] J. M. Hyjazie and C. Wang, “An approach for improving the speed of content addressable memories,” in Proc. IEEE Int. Symp. Circuits Syst.(ISCAS), vol. 5, 2003, pp. 177–180. [23] Igor Arsovski and Ali Sheikholeslami, “A Mismatch-Dependent Power Allocation Technique for Match-Line Sensing in Content-Addressable Memories”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 11, NOVEMBER 2003, pp 1958-1962 [24] N. Mohan, W. Fung, D. Wright, and M. Sachdev, “A ternary CAM with positivefeedback match line sense amplifiers and a match-token priority encoding scheme,” submitted to IEEE Journal of Solid-State Circuits. [25] H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, K. Yamamoto, H. J. Mattausch, T. Koide, A. Amo, A. Hachisuka, S. Soeda, I. Hayashi, F. Morishita, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, “Acost-efficient high-performance dynamic TCAM with pipelined 66 hierarchical search and shift redudancy architecture,” IEEE J. Solid- State Circuits, vol. 40, no. 1, pp. 245–253, Jan. 2005. [26] H. Noda, K. Inoue, M.Kuroiwa, A. Amo, A. Hachisuka, H. J. Mattausch, T. Koide, S. Soeda, K. Dosaka, and K. Arimoto, “A 143 MHz 1.1W4.5 Mb dynamic TCAM with hierarchical searching and shift redundancy architecture,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 208–209. | en_US |
dc.identifier.uri | http://hdl.handle.net/123456789/1248 | |
dc.description | Supervised by Syed Iftekhar Ali, Assistant Professor, Islamic University of Technology (IUT) Organization of the Islamic Cooperation (OIC) Gazipur, Bangladesh | en_US |
dc.description.abstract | Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers especially in internet applications. Despite the attractive features of TCAMs, high power consumption is one of the most critical drawbacks of TCAM. Hence reducing the power consumption without sacrificing the speed and voltage margin is the most difficult part in TCAM design. Among different match line sensing schemes, the use of positive feedback in the sense amplifiers is one of the best solutions to this problem. The main feather of this work is to perform comparison among different existing positive feedback based match line sensing schemes, i.e., mismatch dependent, active feedback and resistive feedback schemes using four performance parameters which are (i) search time (ii) voltage margin (iii) peak dynamic power and (iv)worst case energy consumption. All the schemes are simulated using 130nm, 1.2V CMOS logic. It is shown in this work that the energy saving is maximum (68.77%) in resistive feedback scheme compared to conventional CR-MLSA. Again, comparing among the positive feedback based schemes it is found that the resistive feedback provides with the best speed. Mismatch dependent scheme provides the best voltage margin and peak dynamic power. The worst case energy consumption is least in Active feedback scheme among all three positive feedback based scheme. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Department of Electrical and Electronic Engineering, Islamic University of Technology (IUT), Board Bazar, Gazipur-1704, Bangladesh | en_US |
dc.title | Study & Performance Comparison of Positive Feedback Match-Line (ML) Sensing Schemes for Low Power TCAM | en_US |
dc.type | Thesis | en_US |