Abstract:
The shrinking feature sizes in CMOS-based technologies pose challenges,
prompting a need for more efficient computing architectures. Memristor-based ternary
content addressable (MTCAM) offers a promising alternative to conventional MOSFET based TCAM by offering a promising avenue for high-speed data searching and matching
with reduced power consumption. TCAM's ternary format enables flexible data searching,
vital for networking, pattern recognition, and security applications. However,
conventional TCAM suffers from high costs, chip size, and power consumption. MTCAM
presents a solution, offering scalability and efficiency to meet modern computing
demands. The work presents a novel MTCAM design aimed at high-speed and low-power
applications. This MTCAM structure, comprising of five transistors and four memristors,
offers a unique approach to data preservation. By integrating WRITE and SEARCH
operations on the same lines, the design addresses potential data overwrite issues during
SEARCH operations through a dedicated data recall unit. Moreover, the architecture
employs a consistent voltage level for both WRITE and SEARCH operations, thereby
enhancing efficiency. The study conducted using HSpice simulations for a 32-word array,
each containing 144 MTCAM cells, using 32nm 0.9V strained Si technology models.
Employing a precharge-low current race (CR) match-line scheme, the simulations yielded
impressive results: a search time of 215ps and search energy of 0.556fJ/digit/search for
worst-case mismatches at a supply voltage of 1.2V, along with a substantial voltage
margin of 343mV. Comparative analysis with conventional MOSFET-based TCAM and
other existing designs signifies the superiority of the proposed MTCAM. It exhibits
remarkable reductions in search delay (83%), search energy consumption (61%), voltage
margin (14%), peak power consumption (65%), and estimated area (53%) compared to
conventional MOSFET-based TCAM. Furthermore, it boasts improvements in search
delay (55%), search energy efficiency (18%), voltage margin (7%), and peak power
consumption (10%) compared to the latest existing MTCAM design. Notably, the area
footprint of the proposed MTCAM cell is significantly smaller than that of other designs,
making it a viable option for integrated circuit applications.
Description:
Supervised by
Dr. Syed Iftekhar Ali,
Professor,
Department of Electrical and Electronic Engineering (EEE)
Islamic University of Technology (IUT)
Board Bazar, Gazipur, Bangladesh
This thesis is submitted in partial fulfillment of the requirement for the degree of Doctor of Philosophy in Electrical and Electronic Engineering, 2024