Structure and Operation of Single Electron Transistor and Its Circuit Implementation

Abstract

CMOS Technology has advanced for decades under the rule of Moores law. But all good things must come to an end. Researchers estimate that CMOS will reach a lower limit on feature size within the next 7 to 10 years. In order to assure further progress in the eld, new computing architectures must be investigated. These nanoscale architectures are many and varied. It remains to be seen if any will become a legitimate successor to CMOS. Single electron tunneling is a process by which electrons can be transported (tunnel) across a thin insulating surface. SETs exhibit higher functionality than traditional MOSFETs, and function best at very small feature sizes, in the neigh- borhood of 1nm. SETs have several advantages over MOSFETs. One of the most important of these advantages is low power consumption. Power consumption level of SET is ultra-low. As for example, in this thesis work all the simulation have been done with 35mV supply voltage, whereas the supply voltage of MOSFET based digital circuits is in 3.5V - 12V range. This advantage gives SETs a new ground to develop its eld in VLSI circuits. Many circuits must be developed before SETs can be con- sidered a viable contender to CMOS technology. In this thesis work several digital circuits such as Inverter, 2-input NAND Gate, 2-input NOR Gate, Half Adder and Full Adder have been discussed. All the circuits have been built using complemen- tary logic. For this Complementary Single Electron Transistors (CSET) were used. We propose four possible SET Inverters designs and characterize them with a PSPICE SET simulation model developed by Professor Gnther Lientschnig, Pro- fessor Irek Weymann and Professor Peter Hadley. Among them we chose the best one. Then that bias was used in the next digital circuits.